John H. Lau, Ph.D., P.E. has been the CTO of Unimicron in Taiwan since August 2019. Prior to that, he was a Senior Technical Advisor at ASM Pacific Technology in Hong Kong for 5 years; a specialist of the Industrial Technology Research Institute in Taiwan for 4¿ years and a Senior Scientist/MTS at Hewlett-Packard Laboratory/Agilent in California for more than 25 years. He earrned a Ph.D. degree in theoretical and applied mechanics from the University of Illinois at Urbana-Champaign.With more than 40 years of R&D and manufacturing experience, he has authored or coauthored more than 480 peer-reviewed technical publications, invented more than 30 issued or pending US patents, and given more than 300 lectures/workshops/keynotes worldwide. He has authored or coauthored 20 textbooks on fan-out wafer-level packaging, 3D IC heterogeneous integration and packaging, TSV for 3D integration, advanced MEMS packaging, reliability of 2D and 3D IC interconnects, flip chip, WLP, MCM, area-array packages, WLCSP, high-density PCB, SMT, DCA, TAB, lead-free materials, soldering, manufacturing, and solder joint reliability.He has received many awards from the American Society of Mechanical Engineers (ASME), the Institute of Electrical and Electronics Engineers (IEEE), the Society of Manufacturing Engineers (SME) and other societies. He is an elected ASME fellow, IEEE fellow, and IMAPS fellow, and has been heavily involved in many of ASME's, IEEE's, and IMAPS' technical activities.

Addresses advanced semiconductor packaging both in theory and practice

Comprehensively studies design, materials, process, fabrication, and reliability of various advanced semiconductor packaging technologies

Provides in-depth treatment of packaging technologies

Recent Advance on Semiconductor Packaging.- System-in-Package.- Fan-In Wafer/Panel-Level Chip-Scale Packages.- Fan-Out Wafer/Panel-Level Packaging.- 2D, 2.1D, and 2.3D IC Integration.- 2.5D IC Integration.- 3D IC Integration.- Hybrid Bonding.- Chiplets Packaging.- Dielectric Materials.- Trends and Roadmap for Advanced Semiconductor Packaging.