SystemVerilog for Hardware Description | Buch

Cover: 9789811544040 | SystemVerilog for Hardware Description | RTL Design and Verification

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Sprache: Englisch

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Beschreibung

This book introduces the reader to FPGA based design for RTL synthesis. It describes simple to complex RTL design scenarios using SystemVerilog. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog. It provides practical information on the issues in the RTL design and verification and how to overcome these. It focuses on writing efficient RTL codes using SystemVerilog, covers design for the Xilinx FPGAs and also includes implementable code examples. The contents of this book cover improvement of design performance, assertion based verification, verification planning, and architecture and system testing using FPGAs. The book can be used for classroom teaching or as a supplement in lab work for undergraduate and graduate coursework as well as for professional development and training programs. It will also be of interest to researchers and professionals interested in the RTL design for FPGA and ASIC.

Über den Autor

Vaibbhav Taraate is an entrepreneur and mentor at "Semiconductor Training @ Rs. 1". He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur in 1995. He completed his M.Tech. (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high speed VLSI designs, and architecture design of complex SOCs.

Zusammenfassung

Presents unique view of interpreting FPGA design using SystemVerilog

Includes practical scenarios and issues useful to professionals

Provides over 100 practical examples for design and verification

Covers key case studies in the generic form and design implementation using FPGAs

Inhaltsverzeichnis

Chapter 1: Introduction to FPGA design.- Chapter 2: Introduction to HDL.- Chapter 3:Introduction to SystemVerilog.- Chapter 4: Programming using SystemVerilog.- Chapter 5:Combinational design using SystemVerilog.- Chapter 6: Sequential design using SystemVerilog.- Chapter 7: RTL design using SystemVerilog.- Chapter 8: Verification using SystemVerilog.- Chapter 9: Design Implementation using FPGA.

Details

Erscheinungsjahr:	2020
Fachbereich:	Nachrichtentechnik
Genre:	Technik
Rubrik:	Naturwissenschaften & Technik
Medium:	Buch
Inhalt:	xxi 252 S. 9 s/w Illustr. 95 farbige Illustr. 252 p. 104 illus. 95 illus. in color.
ISBN-13:	9789811544040
ISBN-10:	9811544042
Sprache:	Englisch
Ausstattung / Beilage:	HC runder Rücken kaschiert
Einband:	Gebunden
Autor:	Taraate, Vaibbhav
Auflage:	1st ed. 2020
Hersteller:	Springer Nature Singapore Springer Malaysia Representative Office
Maße:	241 x 160 x 21 mm
Von/Mit:	Vaibbhav Taraate
Erscheinungsdatum:	11.06.2020
Gewicht:	0,582 kg

Artikel-ID: 118106769