Ben Ashbaugh is a Software Architect at Intel Corporation, where he has worked for over 20 years developing software drivers and compilers for Intel graphics products. For the past 10 years, he has focused on parallel programming models for general-purpose computation on graphics processors, including SYCL and the DPC++ compiler. He is active in the Khronos SYCL, OpenCL, and SPIR working groups; helping to define industry standards for parallel programming; and he has authored numerous extensions to expose unique Intel GPU features.

James Brodman is a Principal Engineer at Intel Corporation, working on runtimes and compilers for parallel programming, and he is one of the architects of DPC++. He has a PhD in Computer Science from the University of Illinois at Urbana-Champaign.

Michael Kinsner is a Principal Engineer at Intel Corporation, developing parallel programming languages and compilers for a variety of architectures. He contributes extensively to spatial architectures and programming models and is an Intel representative within The Khronos Group where he works on the SYCL and OpenCL industry standards for parallel programming. He has a PhD in Computer Engineering from McMaster University and is passionate about programming models that cross architectures while still enabling performance.

John Pennycook is a Software Enabling and Optimization Architect at Intel Corporation, focused on enabling developers to fully utilize the parallelism available in modern processors. He is experienced in optimizing and parallelizing applications from a range of scientific domains, and previously served as Intel's representative on the steering committee for the Intel eXtreme Performance User's Group (IXPUG). He has a PhD in Computer Science from the University of Warwick. His research interests are varied, but a recurring theme is the ability to achieve application "performance portability" across different hardware architectures.

Xinmin Tian is an Intel Fellow and Compiler Architect at Intel Corporation and serves as Intel's representative on OpenMP Architecture Review Board (ARB). He has been driving OpenMP offloading, vectorization, and parallelization compiler technologies for Intel architectures. His current focus is on LLVM-based OpenMP offloading, SYCL/DPC++ compiler optimizations for CPUs/GPUs, and tuning HPC/AI application performance. He has a PhD in Computer Science from Tsinghua University, holds 27 US patents, has published over 60 technical papers with over 1300+ citations of his work, and has co-authored two books that span his expertise.