David Money Harris Associate Professor of Engineering at Harvey Mudd College in Claremont, CA, holds a Ph.D. from Stanford University and S.B. and M.Eng. degrees from MIT. His research interests include CMOS VLSI design, microprocessors, and computer arithmetic. He holds a dozen patents, is the author of three other books in the field of digital design and three hiking guidebooks, and has designed chips at Sun Microsystems, Intel, Hewlett-Packard, and Evans & Sutherland.

Neil Weste is a member of the faculty at the Department of Electronic Engineering, Macquarie University; Adjunct Professor of Electrical Engineering at The University of Adelaide; and Director, Engineering at Cisco’s Wireless Networking Business Unit. He is a Fellow of the IEEE for his contributions to custom IC design, and a peer elected member of the IEEE Solid State Circuits Society. In 1997 he cofounded Radiata Communications (with David Skellern) which designed the first chip sets for the IEEE 802.11a WLAN standard; in 2001 Radiata was acquired by Cisco. He has served as department head at Bell Laboratories; leader of design projects for Symbolics, Inc.; and as president of TLW, Inc., an IC engineering company that completed groundbreaking chip designs for companies such as North American Philips, Analog Devices, AT&T Microelectronics and Thomson Consumer Electronics.

Chapter 1 Introduction
1.1 A Brief History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Preview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 MOS Transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 CMOS Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4.1 The Inverter 9
1.4.2 The NAND Gate 9
1.4.3 CMOS Logic Gates 9
1.4.4 The NOR Gate 11
1.4.5 Compound Gates 11
1.4.6 Pass Transistors and Transmission Gates 12
1.4.7 Tristates 14
1.4.8 Multiplexers 15
1.4.9 Sequential Circuits 16
1.5 CMOS Fabrication and Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.1 Inverter Cross-Section 19
1.5.2 Fabrication Process 20
1.5.3 Layout Design Rules 24
1.5.4 Gate Layouts 27
1.5.5 Stick Diagrams 28
1.6 Design Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.6.1 Design Abstractions 30
1.6.2 Structured Design 31
1.6.3 Behavioral, Structural, and Physical Domains 31
1.7 Example: A Simple MIPS Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.7.1 MIPS Architecture 33
1.7.2 Multicycle MIPS Microarchitectures 34
1.8 Logic Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.8.1 Top-Level Interfaces 38
1.8.2 Block Diagrams 38
1.8.3 Hierarchy 40
1.8.4 Hardware Description Languages 40
1.9 Circuit Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
1.10 Physical Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
1.10.1 Floorplanning 45
1.10.2 Standard Cells 48
1.10.3 Pitch Matching 50
1.10.4 Slice Plans 50
1.10.5 Arrays 51
1.10.6 Area Estimation 51
1.11 Design Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
1.12 Fabrication, Packaging, and Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Summary and a Look Ahead 55
Exercises 57

Chapter 2 MOS Transistor Theory
2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.2 Long-Channel I-V Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3 C-V Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.1 Simple MOS Capacitance Models 68
2.3.2 Detailed MOS Gate Capacitance Model 70
2.3.3 Detailed MOS Diffusion Capacitance Model 72
2.4 Nonideal I-V Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.4.1 Mobility Degradation and Velocity Saturation 75
2.4.2 Channel Length Modulation 78
2.4.3 Threshold Voltage Effects 79
2.4.4 Leakage 80
2.4.5 Temperature Dependence 85
2.4.6 Geometry Dependence 86
2.4.7 Summary 86
2.5 DC Transfer Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.5.1 Static CMOS Inverter DC Characteristics 88
2.5.2 Beta Ratio Effects 90
2.5.3 Noise Margin 91
2.5.4 Pass Transistor DC Characteristics 92
2.6 Pitfalls and Fallacies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Summary 94
Exercises 95

Chapter 3 CMOS Processing Technology
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.2 CMOS Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.2.1 Wafer Formation 100
3.2.2 Photolithography 101
3.2.3 Well and Channel Formation 103
3.2.4 Silicon Dioxide (SiO2) 105
3.2.5 Isolation 106
3.2.6 Gate Oxide 107
3.2.7 Gate and Source/Drain Formations 108
3.2.8 Contacts and Metallization 110
3.2.9 Passivation 112
3.2.10 Metrology 112
3.3 Layout Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.3.1 Design Rule Background 113
3.3.2 Scribe Line and Other Structures 116
3.3.3 MOSIS Scalable CMOS Design Rules 117
3.3.4 Micron Design Rules 118
3.4 CMOS Process Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
3.4.1 Transistors 119
3.4.2 Interconnect 122
3.4.3 Circuit Elements 124
3.4.4 Beyond Conventional CMOS 129
3.5 Technology-Related CAD Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
3.5.1 Design Rule Checking (DRC) 131
3.5.2 Circuit Extraction 132
3.6 Manufacturing Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
3.6.1 Antenna Rules 133
3.6.2 Layer Density Rules 134
3.6.3 Resolution Enhancement Rules 134
3.6.4 Metal Slotting Rules 135
3.6.5 Yield Enhancement Guidelines 135
3.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
3.8 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Summary 139
Exercises 139

Chapter 4 Delay
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
4.1.1 Definitions 141
4.1.2 Timing Optimization 142
4.2 Transient Response . . . . . . . . . . . . . . . . . . . . . . . 143
4.3 RC Delay Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
4.3.1 Effective Resistance 146
4.3.2 Gate and Diffusion Capacitance 147
4.3.3 Equivalent RC Circuits 147
4.3.4 Transient Response 148
4.3.5 Elmore Delay 150
4.3.6 Layout Dependence of Capacitance 153
4.3.7 Determining Effective Resistance 154
4.4 Linear Delay Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.4.1 Logical Effort 156
4.4.2 Parasitic Delay 156
4.4.3 Delay in a Logic Gate 158
4.4.4 Drive 159
4.4.5 Extracting Logical Effort from Datasheets 159
4.4.6 Limitations to the Linear Delay Model 160
4.5 Logical Effort of Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
4.5.1 Delay in Multistage Logic Networks 163
4.5.2 Choosing the Best Number of Stages 166
4.5.3 Example 168
4.5.4 Summary and Observations 169
4.5.5 Limitations of Logical Effort 171
4.5.6 Iterative Solutions for Sizing 171
4.6 Timing Analysis Delay Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
4.6.1 Slope-Based Linear Model 173
4.6.2 Nonlinear Delay Model 174
4.6.3 Current Source Model 174
4.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
4.8 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Summary 176
Exercises 176

Chapter 5 Power
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.1.1 Definitions 182
5.1.2 Examples 182
5.1.3 Sources of Power Dissipation 184
5.2 Dynamic Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
5.2.1 Activity Factor 186
5.2.2 Capacitance 188
5.2.3 Voltage 190
5.2.4 Frequency 192
5.2.5 Short-Circuit Current 193
5.2.6 Resonant Circuits 193
5.3 Static Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
5.3.1 Static Power Sources 194
5.3.2 Power Gating 197
5.3.3 Multiple Threshold Voltages and Oxide Thicknesses 19
5.3.4 Variable Threshold Voltages 199
5.3.5 Input Vector Control 200
5.4 Energy-Delay Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
5.4.1 Minimum Energy 200
5.4.2 Minimum Energy-Delay Product 203
5.4.3 Minimum Energy Under a Delay Constraint 203
5.5 Low Power Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
5.5.1 Microarchitecture 204
5.5.2 Parallelism and Pipelining 204
5.5.3 Power Management Modes 205
5.6 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
5.7 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Summary 209
Exercises 209

Chapter 6 Interconnect
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
6.1.1 Wire Geometry 211
6.1.2 Example: Intel Metal Stacks 212
6.2 Interconnect Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
6.2.1 Resistance 214
6.2.2 Capacitance 215
6.2.3 Inductance 218
6.2.4 Skin Effect 219
6.2.5 Temperature Dependence 220
6.3 Interconnect Impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
6.3.1 Delay 220
6.3.2 Energy 222
6.3.3 Crosstalk 222
6.3.4 Inductive Effects 224
6.3.5 An Aside on Effective Resistance and Elmore Delay 227
6.4 Interconnect Engineering . . . . . . . . . . . . . . . . . ....