J. Bhasker is a well-known expert in the area of hardware description languages and RTL synthesis. He has been chair of two working groups: the IEEE 1076.6 VHDL Synthesis and the IEEE 1364.1 Verilog Synthesis and was awarded the IEEE Computer Society Outstanding Contribution Award in 2005. He is an architect at eSilicon Corporation responsible for the timing of many complex designs.

Rakesh Chadha is a CAE and Design Professional with over 25 years experience, including 18 years in project leadership and technical management. He was responsible for the timing and signal integrity for the Sematech project on Chip Parasitic Extraction and Signal Integrity Verification. He is Director of Design Technology at eSilicon Corporation and is responsible for complex SOC design methodology.

Starts from the ground-up and explains what power is, how it is measured and how it impacts on the ASIC design process

Provides essential information in an easy to read and understand format, using basic examples

Explains what power intent is, how to describe it precisely and what techniques can be used to achieve the power intent with the two key standards, the Unified Power Format (UPF) and Common Power Format (CPF)

Introduction.- Modeling of Power in Core Logic.- Modeling of Power in IOS and Micro Blocks.- Power and Analysis in ASCIS.- Design Intent for Power Management.- Architectural Techniques for Low Power.- Low Power Implementation Techniques.- UPF Power Specification.- CPF Power Specification.- Appendix A.- Appendix B.- Bibliography.- Index.