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Cover: 9781441941251 | SystemVerilog for Design Second Edition | Stuart Sutherland (u. a.)
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SystemVerilog for Design Second Edition
A Guide to Using SystemVerilog for Hardware Design and Modeling
Taschenbuch von Stuart Sutherland (u. a.)
Sprache: Englisch

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Beschreibung
SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs.

The first edition of this book addressed the first aspect of the SystemVerilog extensions to Verilog. Important modeling features were presented, such as two-state data types, enumerated types, user-degined types, structures, unions, and interfaces. Emphasis was placed on the proper usage of these enhancements for simulation and synthesis.

SystemVerilog for Design, Second Edition has been extensively revised on a chapter by chapter basis to include the many text and example updates needed to reflect changes that were made between the first edition of this book was written and the finalization of the new standard. It is important that the book reflect these syntax and semantic changes to the SystemVerilog language.

In addition, the second edition features a new chapter that explanis the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools.
SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs.

The first edition of this book addressed the first aspect of the SystemVerilog extensions to Verilog. Important modeling features were presented, such as two-state data types, enumerated types, user-degined types, structures, unions, and interfaces. Emphasis was placed on the proper usage of these enhancements for simulation and synthesis.

SystemVerilog for Design, Second Edition has been extensively revised on a chapter by chapter basis to include the many text and example updates needed to reflect changes that were made between the first edition of this book was written and the finalization of the new standard. It is important that the book reflect these syntax and semantic changes to the SystemVerilog language.

In addition, the second edition features a new chapter that explanis the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools.
Zusammenfassung
In its updated second edition, this book has been extensively revised on a chapter by chapter basis to include the many text and example updates needed to reflect changes adopted between the first edition of the book and the finalization of the new standard. The book accurately reflects the syntax and semantic changes to the SystemVerilog language, making it an essential reference for systems professionals who need the latest version information. In addition, the second edition features a new chapter that explains the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools.
Inhaltsverzeichnis
to SystemVerilog.- SystemVerilog Declaration Spaces.- SystemVerilog Literal Values and Built-in Data Types.- SystemVerilog User-Defined and Enumerated Types.- SystemVerilog Arrays, Structures and Unions.- SystemVerilog Procedural Blocks, Tasks and Functions.- SystemVerilog Procedural Statements.- Modeling Finite State Machines with SystemVerilog.- SystemVerilog Design Hierarchy.- SystemVerilog Interfaces.- A Complete Design Modeled with SystemVerilog.- Behavioral and Transaction Level Modeling.
Details
Erscheinungsjahr: 2010
Fachbereich: Nachrichtentechnik
Genre: Technik
Rubrik: Naturwissenschaften & Technik
Medium: Taschenbuch
Inhalt: xxx
418 S.
ISBN-13: 9781441941251
ISBN-10: 1441941258
Sprache: Englisch
Ausstattung / Beilage: Paperback
Einband: Kartoniert / Broschiert
Autor: Sutherland, Stuart
Flake, Peter
Davidmann, Simon
Auflage: Second Edition 2006
Hersteller: Springer US
Springer US, New York, N.Y.
Maße: 235 x 155 x 25 mm
Von/Mit: Stuart Sutherland (u. a.)
Erscheinungsdatum: 29.10.2010
Gewicht: 0,674 kg
Artikel-ID: 107252271
Zusammenfassung
In its updated second edition, this book has been extensively revised on a chapter by chapter basis to include the many text and example updates needed to reflect changes adopted between the first edition of the book and the finalization of the new standard. The book accurately reflects the syntax and semantic changes to the SystemVerilog language, making it an essential reference for systems professionals who need the latest version information. In addition, the second edition features a new chapter that explains the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools.
Inhaltsverzeichnis
to SystemVerilog.- SystemVerilog Declaration Spaces.- SystemVerilog Literal Values and Built-in Data Types.- SystemVerilog User-Defined and Enumerated Types.- SystemVerilog Arrays, Structures and Unions.- SystemVerilog Procedural Blocks, Tasks and Functions.- SystemVerilog Procedural Statements.- Modeling Finite State Machines with SystemVerilog.- SystemVerilog Design Hierarchy.- SystemVerilog Interfaces.- A Complete Design Modeled with SystemVerilog.- Behavioral and Transaction Level Modeling.
Details
Erscheinungsjahr: 2010
Fachbereich: Nachrichtentechnik
Genre: Technik
Rubrik: Naturwissenschaften & Technik
Medium: Taschenbuch
Inhalt: xxx
418 S.
ISBN-13: 9781441941251
ISBN-10: 1441941258
Sprache: Englisch
Ausstattung / Beilage: Paperback
Einband: Kartoniert / Broschiert
Autor: Sutherland, Stuart
Flake, Peter
Davidmann, Simon
Auflage: Second Edition 2006
Hersteller: Springer US
Springer US, New York, N.Y.
Maße: 235 x 155 x 25 mm
Von/Mit: Stuart Sutherland (u. a.)
Erscheinungsdatum: 29.10.2010
Gewicht: 0,674 kg
Artikel-ID: 107252271
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