Low Power Design with High-Level Power Est...

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Sprache: Englisch

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Beschreibung

This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

Zusammenfassung

Integrates power estimation and reduction for high level synthesis, with low-power, high-level design

Shows specific techniques for ASICs as well as FPGA based SoC designs, allowing readers to evaluate and explore various possible alternatives

Covers techniques from RTL/gate-level to hardware software co-design

Inhaltsverzeichnis

Introduction.- Related Work.- Background.- Architectural Selection using High Level Synthesis.- Statistical Regression Based Power Models.- Coprocessor Design Space Exploration Using High Level Synthesis.- Regression-based Dynamic Power Estimation for FPGAs.- High Level Simulation Directed RTL Power Estimation.- Applying Verification Collaterals for Accurate Power Estimation.- Power Reduction using High-Level Clock-gating.- Model-Checking to exploit Sequential Clock-gating.- System Level Simulation Guided Approach for Clock-gating.- Conclusions.

Details

Erscheinungsjahr:	2014
Fachbereich:	Nachrichtentechnik
Genre:	Importe , Technik
Rubrik:	Naturwissenschaften & Technik
Medium:	Taschenbuch
Inhalt:	xxii 170 S.
ISBN-13:	9781489987808
ISBN-10:	1489987800
Sprache:	Englisch
Einband:	Kartoniert / Broschiert
Autor:	Ahuja, Sumit Lakshminarayana, Avinash Shukla, Sandeep Kumar
Hersteller:	Springer Springer US, New York, N.Y.
Verantwortliche Person für die EU:	Springer Verlag GmbH, Tiergartenstr. 17, D-69121 Heidelberg, juergen.hartmann@springer.com
Maße:	235 x 155 x 11 mm
Von/Mit:	Sumit Ahuja (u. a.)
Erscheinungsdatum:	23.10.2014
Gewicht:	0,3 kg