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A hands-on introduction to FPGA prototyping and SoC design
This Second Edition of the popular book follows the same "learning-by-doing" approach to teach the fundamentals and practices of VHDL synthesis and FPGA prototyping. It uses a coherent series of examples to demonstrate the process to develop sophisticated digital circuits and IP (intellectual property) cores, integrate them into an SoC (system on a chip) framework, realize the system on an FPGA prototyping board, and verify the hardware and software operation. The examples start with simple gate-level circuits, progress gradually through the RT (register transfer) level modules, and lead to a functional embedded system with custom I/O peripherals and hardware accelerators. Although it is an introductory text, the examples are developed in a rigorous manner, and the derivations follow strict design guidelines and coding practices used for large, complex digital systems.
The new edition is completely updated. It presents the hardware design in the SoC context and introduces the hardware-software co-design concept. Instead of treating examples as isolated entities, the book integrates them into a single coherent SoC platform that allows readers to explore both hardware and software "programmability" and develop complex and interesting embedded system projects. The revised edition:
* Adds four general-purpose IP cores, which are multi-channel PWM (pulse width modulation) controller, I²C controller, SPI controller, and XADC (Xilinx analog-to-digital converter) controller.
* Introduces a music synthesizer constructed with a DDFS (direct digital frequency synthesis) module and an ADSR (attack-decay-sustain-release) envelop generator.
* Expands the original video controller into a complete stream-based video subsystem that incorporates a video synchronization circuit, a test pattern generator, an OSD (on-screen display) controller, a sprite generator, and a frame buffer.
* Introduces basic concepts of software-hardware co-design with Xilinx MicroBlaze MCS soft-core processor.
* Provides an overview of bus interconnect and interface circuit.
* Introduces basic embedded system software development.
* Suggests additional modules and peripherals for interesting and challenging projects.
The FPGA Prototyping by VHDL Examples, Second Edition makes a natural companion text for introductory and advanced digital design courses and embedded system course. It also serves as an ideal self-teaching guide for practicing engineers who wish to learn more about this emerging area of interest.
This Second Edition of the popular book follows the same "learning-by-doing" approach to teach the fundamentals and practices of VHDL synthesis and FPGA prototyping. It uses a coherent series of examples to demonstrate the process to develop sophisticated digital circuits and IP (intellectual property) cores, integrate them into an SoC (system on a chip) framework, realize the system on an FPGA prototyping board, and verify the hardware and software operation. The examples start with simple gate-level circuits, progress gradually through the RT (register transfer) level modules, and lead to a functional embedded system with custom I/O peripherals and hardware accelerators. Although it is an introductory text, the examples are developed in a rigorous manner, and the derivations follow strict design guidelines and coding practices used for large, complex digital systems.
The new edition is completely updated. It presents the hardware design in the SoC context and introduces the hardware-software co-design concept. Instead of treating examples as isolated entities, the book integrates them into a single coherent SoC platform that allows readers to explore both hardware and software "programmability" and develop complex and interesting embedded system projects. The revised edition:
* Adds four general-purpose IP cores, which are multi-channel PWM (pulse width modulation) controller, I²C controller, SPI controller, and XADC (Xilinx analog-to-digital converter) controller.
* Introduces a music synthesizer constructed with a DDFS (direct digital frequency synthesis) module and an ADSR (attack-decay-sustain-release) envelop generator.
* Expands the original video controller into a complete stream-based video subsystem that incorporates a video synchronization circuit, a test pattern generator, an OSD (on-screen display) controller, a sprite generator, and a frame buffer.
* Introduces basic concepts of software-hardware co-design with Xilinx MicroBlaze MCS soft-core processor.
* Provides an overview of bus interconnect and interface circuit.
* Introduces basic embedded system software development.
* Suggests additional modules and peripherals for interesting and challenging projects.
The FPGA Prototyping by VHDL Examples, Second Edition makes a natural companion text for introductory and advanced digital design courses and embedded system course. It also serves as an ideal self-teaching guide for practicing engineers who wish to learn more about this emerging area of interest.
A hands-on introduction to FPGA prototyping and SoC design
This Second Edition of the popular book follows the same "learning-by-doing" approach to teach the fundamentals and practices of VHDL synthesis and FPGA prototyping. It uses a coherent series of examples to demonstrate the process to develop sophisticated digital circuits and IP (intellectual property) cores, integrate them into an SoC (system on a chip) framework, realize the system on an FPGA prototyping board, and verify the hardware and software operation. The examples start with simple gate-level circuits, progress gradually through the RT (register transfer) level modules, and lead to a functional embedded system with custom I/O peripherals and hardware accelerators. Although it is an introductory text, the examples are developed in a rigorous manner, and the derivations follow strict design guidelines and coding practices used for large, complex digital systems.
The new edition is completely updated. It presents the hardware design in the SoC context and introduces the hardware-software co-design concept. Instead of treating examples as isolated entities, the book integrates them into a single coherent SoC platform that allows readers to explore both hardware and software "programmability" and develop complex and interesting embedded system projects. The revised edition:
* Adds four general-purpose IP cores, which are multi-channel PWM (pulse width modulation) controller, I²C controller, SPI controller, and XADC (Xilinx analog-to-digital converter) controller.
* Introduces a music synthesizer constructed with a DDFS (direct digital frequency synthesis) module and an ADSR (attack-decay-sustain-release) envelop generator.
* Expands the original video controller into a complete stream-based video subsystem that incorporates a video synchronization circuit, a test pattern generator, an OSD (on-screen display) controller, a sprite generator, and a frame buffer.
* Introduces basic concepts of software-hardware co-design with Xilinx MicroBlaze MCS soft-core processor.
* Provides an overview of bus interconnect and interface circuit.
* Introduces basic embedded system software development.
* Suggests additional modules and peripherals for interesting and challenging projects.
The FPGA Prototyping by VHDL Examples, Second Edition makes a natural companion text for introductory and advanced digital design courses and embedded system course. It also serves as an ideal self-teaching guide for practicing engineers who wish to learn more about this emerging area of interest.
This Second Edition of the popular book follows the same "learning-by-doing" approach to teach the fundamentals and practices of VHDL synthesis and FPGA prototyping. It uses a coherent series of examples to demonstrate the process to develop sophisticated digital circuits and IP (intellectual property) cores, integrate them into an SoC (system on a chip) framework, realize the system on an FPGA prototyping board, and verify the hardware and software operation. The examples start with simple gate-level circuits, progress gradually through the RT (register transfer) level modules, and lead to a functional embedded system with custom I/O peripherals and hardware accelerators. Although it is an introductory text, the examples are developed in a rigorous manner, and the derivations follow strict design guidelines and coding practices used for large, complex digital systems.
The new edition is completely updated. It presents the hardware design in the SoC context and introduces the hardware-software co-design concept. Instead of treating examples as isolated entities, the book integrates them into a single coherent SoC platform that allows readers to explore both hardware and software "programmability" and develop complex and interesting embedded system projects. The revised edition:
* Adds four general-purpose IP cores, which are multi-channel PWM (pulse width modulation) controller, I²C controller, SPI controller, and XADC (Xilinx analog-to-digital converter) controller.
* Introduces a music synthesizer constructed with a DDFS (direct digital frequency synthesis) module and an ADSR (attack-decay-sustain-release) envelop generator.
* Expands the original video controller into a complete stream-based video subsystem that incorporates a video synchronization circuit, a test pattern generator, an OSD (on-screen display) controller, a sprite generator, and a frame buffer.
* Introduces basic concepts of software-hardware co-design with Xilinx MicroBlaze MCS soft-core processor.
* Provides an overview of bus interconnect and interface circuit.
* Introduces basic embedded system software development.
* Suggests additional modules and peripherals for interesting and challenging projects.
The FPGA Prototyping by VHDL Examples, Second Edition makes a natural companion text for introductory and advanced digital design courses and embedded system course. It also serves as an ideal self-teaching guide for practicing engineers who wish to learn more about this emerging area of interest.
Inhaltsverzeichnis
Preface ix
Acknowledgments xv
PART I BASIC DIGITAL CIRCUITS DEVELOPMENT
1 Gate-level Combinational Circuit 1
1.1 Overview of VHDL 1
1.2 General description 2
1.3 Structural description 6
1.4 Top-level signal mapping 8
1.5 Testbench 9
1.6 Bibliographic notes 11
1.7 Suggested experiments 11
2 Overview of FPGA and EDA software 13
2.1 FPGA 13
2.2 Overview of the Digilent Nexys 4 DDR board 15
2.3 Development flow 16
2.4 Xilinx Vivado Design Suite 18
2.5 Bibliographic notes 18
2.6 Suggested experiments 18
3 RT-level combinational circuit 23
3.1 RT-level components 23
3.2 Routing circuit with concurrent assignment statements 29
3.3 Modeling with a process 34
3.4 Routing circuit with if and case statements 36
3.5 Constants and generics 41
3.6 Replicated structure 44
3.7 Design examples 46
3.8 Bibliographic notes 58
3.9 Suggested experiments 58
4 Regular Sequential Circuit 61
4.1 Introduction 61
4.2 HDL code of the FF and register 64
4.3 Simple design examples 67
4.4 Testbench for sequential circuits 72
4.5 Case study 75
4.6 Timing and clocking 87
4.7 Bibliographic notes 90
4.8 Suggested experiments 90
5 FSM 93
5.1 Introduction 93
5.2 FSM code development 97
5.3 Design examples 100
5.4 Bibliographic notes 110
5.5 Suggested experiments 110
6 FSMD 113
6.1 Introduction 113
6.2 Code development of an FSMD 119
6.3 Design examples 125
6.4 Bibliographic notes 140
6.5 Suggested experiments 141
7 RAM and Buffer of FPGA 145
7.1 Embedded memory of FPGA device 145
7.2 General description for RAM-like component 147
7.3 FIFO buffer 153
7.4 HDL templates for memory inference 158
7.5 Overview of memory controller 164
7.6 Bibliographic notes 166
7.7 Suggested experiments 166
PART II EMBEDDED SOC I: VANILLA FPRO SYSTEM
8 Overview of Embedded SoC Systems 171
8.1 Embedded SoC 171
8.2 Development Flow of Embedded SoC 173
8.3 FPro SoC Platform 176
8.4 Adaption on Digilent Nexys 4 DDR board 180
8.5 Portability 182
8.6 Organization 184
8.7 Bibliographic notes 184
9 Bare Metal System Software Development 187
9.1 Bare metal system development overview 187
9.2 Memory-mapped I/O 189
9.3 Direct I/O Register Access 191
9.4 Robust I/O Register Access 193
9.5 Techniques for low-level I/O operations 197
9.6 Device Drivers 199
9.7 FPro Utility Routines and Directory Structure 204
9.8 Test program 208
9.9 Bibliographic notes 211
9.10 Suggested experiments 211
10 FPro Bus Protocol and MMIO Slot Specification 213
10.1 FPro Bus 213
10.2 Interface with bus 216
10.3 MMIO I/O core 222
10.4 Timer core development 226
10.5 MMIO controller 229
10.6 MCS I/O bus and bridge 234
10.7 Vanilla FPRO System Construction 238
10.8 Bibliographic notes 240
10.9 Suggested experiments 240
11 UART Core 243
11.1 Introduction 243
11.2 UART Construction 245
11.3 UART core development 253
11.4 UART driver 256
11.5 Additional
Acknowledgments xv
PART I BASIC DIGITAL CIRCUITS DEVELOPMENT
1 Gate-level Combinational Circuit 1
1.1 Overview of VHDL 1
1.2 General description 2
1.3 Structural description 6
1.4 Top-level signal mapping 8
1.5 Testbench 9
1.6 Bibliographic notes 11
1.7 Suggested experiments 11
2 Overview of FPGA and EDA software 13
2.1 FPGA 13
2.2 Overview of the Digilent Nexys 4 DDR board 15
2.3 Development flow 16
2.4 Xilinx Vivado Design Suite 18
2.5 Bibliographic notes 18
2.6 Suggested experiments 18
3 RT-level combinational circuit 23
3.1 RT-level components 23
3.2 Routing circuit with concurrent assignment statements 29
3.3 Modeling with a process 34
3.4 Routing circuit with if and case statements 36
3.5 Constants and generics 41
3.6 Replicated structure 44
3.7 Design examples 46
3.8 Bibliographic notes 58
3.9 Suggested experiments 58
4 Regular Sequential Circuit 61
4.1 Introduction 61
4.2 HDL code of the FF and register 64
4.3 Simple design examples 67
4.4 Testbench for sequential circuits 72
4.5 Case study 75
4.6 Timing and clocking 87
4.7 Bibliographic notes 90
4.8 Suggested experiments 90
5 FSM 93
5.1 Introduction 93
5.2 FSM code development 97
5.3 Design examples 100
5.4 Bibliographic notes 110
5.5 Suggested experiments 110
6 FSMD 113
6.1 Introduction 113
6.2 Code development of an FSMD 119
6.3 Design examples 125
6.4 Bibliographic notes 140
6.5 Suggested experiments 141
7 RAM and Buffer of FPGA 145
7.1 Embedded memory of FPGA device 145
7.2 General description for RAM-like component 147
7.3 FIFO buffer 153
7.4 HDL templates for memory inference 158
7.5 Overview of memory controller 164
7.6 Bibliographic notes 166
7.7 Suggested experiments 166
PART II EMBEDDED SOC I: VANILLA FPRO SYSTEM
8 Overview of Embedded SoC Systems 171
8.1 Embedded SoC 171
8.2 Development Flow of Embedded SoC 173
8.3 FPro SoC Platform 176
8.4 Adaption on Digilent Nexys 4 DDR board 180
8.5 Portability 182
8.6 Organization 184
8.7 Bibliographic notes 184
9 Bare Metal System Software Development 187
9.1 Bare metal system development overview 187
9.2 Memory-mapped I/O 189
9.3 Direct I/O Register Access 191
9.4 Robust I/O Register Access 193
9.5 Techniques for low-level I/O operations 197
9.6 Device Drivers 199
9.7 FPro Utility Routines and Directory Structure 204
9.8 Test program 208
9.9 Bibliographic notes 211
9.10 Suggested experiments 211
10 FPro Bus Protocol and MMIO Slot Specification 213
10.1 FPro Bus 213
10.2 Interface with bus 216
10.3 MMIO I/O core 222
10.4 Timer core development 226
10.5 MMIO controller 229
10.6 MCS I/O bus and bridge 234
10.7 Vanilla FPRO System Construction 238
10.8 Bibliographic notes 240
10.9 Suggested experiments 240
11 UART Core 243
11.1 Introduction 243
11.2 UART Construction 245
11.3 UART core development 253
11.4 UART driver 256
11.5 Additional
Details
| Erscheinungsjahr: | 2017 |
|---|---|
| Fachbereich: | Nachrichtentechnik |
| Genre: | Technik |
| Rubrik: | Naturwissenschaften & Technik |
| Medium: | Buch |
| Inhalt: | 632 S. |
| ISBN-13: | 9781119282747 |
| ISBN-10: | 1119282748 |
| Sprache: | Englisch |
| Herstellernummer: | 1W119282740 |
| Autor: | Chu, Pong P. |
| Auflage: | 2. Aufl. |
| Hersteller: |
Wiley
Wiley & Sons |
| Maße: | 262 x 178 x 38 mm |
| Von/Mit: | Pong P. Chu |
| Erscheinungsdatum: | 29.12.2017 |
| Gewicht: | 1,261 kg |
Inhaltsverzeichnis
Preface ix
Acknowledgments xv
PART I BASIC DIGITAL CIRCUITS DEVELOPMENT
1 Gate-level Combinational Circuit 1
1.1 Overview of VHDL 1
1.2 General description 2
1.3 Structural description 6
1.4 Top-level signal mapping 8
1.5 Testbench 9
1.6 Bibliographic notes 11
1.7 Suggested experiments 11
2 Overview of FPGA and EDA software 13
2.1 FPGA 13
2.2 Overview of the Digilent Nexys 4 DDR board 15
2.3 Development flow 16
2.4 Xilinx Vivado Design Suite 18
2.5 Bibliographic notes 18
2.6 Suggested experiments 18
3 RT-level combinational circuit 23
3.1 RT-level components 23
3.2 Routing circuit with concurrent assignment statements 29
3.3 Modeling with a process 34
3.4 Routing circuit with if and case statements 36
3.5 Constants and generics 41
3.6 Replicated structure 44
3.7 Design examples 46
3.8 Bibliographic notes 58
3.9 Suggested experiments 58
4 Regular Sequential Circuit 61
4.1 Introduction 61
4.2 HDL code of the FF and register 64
4.3 Simple design examples 67
4.4 Testbench for sequential circuits 72
4.5 Case study 75
4.6 Timing and clocking 87
4.7 Bibliographic notes 90
4.8 Suggested experiments 90
5 FSM 93
5.1 Introduction 93
5.2 FSM code development 97
5.3 Design examples 100
5.4 Bibliographic notes 110
5.5 Suggested experiments 110
6 FSMD 113
6.1 Introduction 113
6.2 Code development of an FSMD 119
6.3 Design examples 125
6.4 Bibliographic notes 140
6.5 Suggested experiments 141
7 RAM and Buffer of FPGA 145
7.1 Embedded memory of FPGA device 145
7.2 General description for RAM-like component 147
7.3 FIFO buffer 153
7.4 HDL templates for memory inference 158
7.5 Overview of memory controller 164
7.6 Bibliographic notes 166
7.7 Suggested experiments 166
PART II EMBEDDED SOC I: VANILLA FPRO SYSTEM
8 Overview of Embedded SoC Systems 171
8.1 Embedded SoC 171
8.2 Development Flow of Embedded SoC 173
8.3 FPro SoC Platform 176
8.4 Adaption on Digilent Nexys 4 DDR board 180
8.5 Portability 182
8.6 Organization 184
8.7 Bibliographic notes 184
9 Bare Metal System Software Development 187
9.1 Bare metal system development overview 187
9.2 Memory-mapped I/O 189
9.3 Direct I/O Register Access 191
9.4 Robust I/O Register Access 193
9.5 Techniques for low-level I/O operations 197
9.6 Device Drivers 199
9.7 FPro Utility Routines and Directory Structure 204
9.8 Test program 208
9.9 Bibliographic notes 211
9.10 Suggested experiments 211
10 FPro Bus Protocol and MMIO Slot Specification 213
10.1 FPro Bus 213
10.2 Interface with bus 216
10.3 MMIO I/O core 222
10.4 Timer core development 226
10.5 MMIO controller 229
10.6 MCS I/O bus and bridge 234
10.7 Vanilla FPRO System Construction 238
10.8 Bibliographic notes 240
10.9 Suggested experiments 240
11 UART Core 243
11.1 Introduction 243
11.2 UART Construction 245
11.3 UART core development 253
11.4 UART driver 256
11.5 Additional
Acknowledgments xv
PART I BASIC DIGITAL CIRCUITS DEVELOPMENT
1 Gate-level Combinational Circuit 1
1.1 Overview of VHDL 1
1.2 General description 2
1.3 Structural description 6
1.4 Top-level signal mapping 8
1.5 Testbench 9
1.6 Bibliographic notes 11
1.7 Suggested experiments 11
2 Overview of FPGA and EDA software 13
2.1 FPGA 13
2.2 Overview of the Digilent Nexys 4 DDR board 15
2.3 Development flow 16
2.4 Xilinx Vivado Design Suite 18
2.5 Bibliographic notes 18
2.6 Suggested experiments 18
3 RT-level combinational circuit 23
3.1 RT-level components 23
3.2 Routing circuit with concurrent assignment statements 29
3.3 Modeling with a process 34
3.4 Routing circuit with if and case statements 36
3.5 Constants and generics 41
3.6 Replicated structure 44
3.7 Design examples 46
3.8 Bibliographic notes 58
3.9 Suggested experiments 58
4 Regular Sequential Circuit 61
4.1 Introduction 61
4.2 HDL code of the FF and register 64
4.3 Simple design examples 67
4.4 Testbench for sequential circuits 72
4.5 Case study 75
4.6 Timing and clocking 87
4.7 Bibliographic notes 90
4.8 Suggested experiments 90
5 FSM 93
5.1 Introduction 93
5.2 FSM code development 97
5.3 Design examples 100
5.4 Bibliographic notes 110
5.5 Suggested experiments 110
6 FSMD 113
6.1 Introduction 113
6.2 Code development of an FSMD 119
6.3 Design examples 125
6.4 Bibliographic notes 140
6.5 Suggested experiments 141
7 RAM and Buffer of FPGA 145
7.1 Embedded memory of FPGA device 145
7.2 General description for RAM-like component 147
7.3 FIFO buffer 153
7.4 HDL templates for memory inference 158
7.5 Overview of memory controller 164
7.6 Bibliographic notes 166
7.7 Suggested experiments 166
PART II EMBEDDED SOC I: VANILLA FPRO SYSTEM
8 Overview of Embedded SoC Systems 171
8.1 Embedded SoC 171
8.2 Development Flow of Embedded SoC 173
8.3 FPro SoC Platform 176
8.4 Adaption on Digilent Nexys 4 DDR board 180
8.5 Portability 182
8.6 Organization 184
8.7 Bibliographic notes 184
9 Bare Metal System Software Development 187
9.1 Bare metal system development overview 187
9.2 Memory-mapped I/O 189
9.3 Direct I/O Register Access 191
9.4 Robust I/O Register Access 193
9.5 Techniques for low-level I/O operations 197
9.6 Device Drivers 199
9.7 FPro Utility Routines and Directory Structure 204
9.8 Test program 208
9.9 Bibliographic notes 211
9.10 Suggested experiments 211
10 FPro Bus Protocol and MMIO Slot Specification 213
10.1 FPro Bus 213
10.2 Interface with bus 216
10.3 MMIO I/O core 222
10.4 Timer core development 226
10.5 MMIO controller 229
10.6 MCS I/O bus and bridge 234
10.7 Vanilla FPRO System Construction 238
10.8 Bibliographic notes 240
10.9 Suggested experiments 240
11 UART Core 243
11.1 Introduction 243
11.2 UART Construction 245
11.3 UART core development 253
11.4 UART driver 256
11.5 Additional
Details
| Erscheinungsjahr: | 2017 |
|---|---|
| Fachbereich: | Nachrichtentechnik |
| Genre: | Technik |
| Rubrik: | Naturwissenschaften & Technik |
| Medium: | Buch |
| Inhalt: | 632 S. |
| ISBN-13: | 9781119282747 |
| ISBN-10: | 1119282748 |
| Sprache: | Englisch |
| Herstellernummer: | 1W119282740 |
| Autor: | Chu, Pong P. |
| Auflage: | 2. Aufl. |
| Hersteller: |
Wiley
Wiley & Sons |
| Maße: | 262 x 178 x 38 mm |
| Von/Mit: | Pong P. Chu |
| Erscheinungsdatum: | 29.12.2017 |
| Gewicht: | 1,261 kg |
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