Wenxiang Wang, Ph.D., senior engineer, is Chief Architect of the processor core at Loongson Technology Co., Ltd., and an adjunct professor at the University of Science and Technology of China. His main research interests include processor architecture design, processor verification, and performance analysis and optimization of computer systems. He has participated in several national "Core Electronics Devices, High-End General-Purpose Chips, and Basic Software Products" (National Major Science and Technology Project), 863, and 973 projects. He has published more than ten papers in domestic and international journals and conferences, applied for dozens of patents, and been granted more than ten patents. Since 2012, he has served as the leader of the IP group in the Chip R&D Department of Loongson Technology, responsible for the development, research, and maintenance of the Loongson series CPU IP cores, and participated in formulating the LoongArch instruction set architecture specifications. He is the author of CPU Design and Practice, Computer Architecture, Fundamentals of Computer Architecture, and other works.

Jinzhang Xing graduated with a master’s degree from the Institute of Computing Technology, Chinese Academy of Sciences. In 2015, he joined Loongson Technology Co., Ltd. He has long been engaged in the research and development of processor core structures and is one of the main structural designers of the Loongson series processor cores. In recent years, he has actively participated in providing technical support and training for the CPU Design Competition (Loongson Cup) of the National Computer System Development Capability Competition.

Chapter 1. Overview of the CPU Chip Development Process.- Chapter 2. Hardware Experiment Platform and FPGA Design Flow.- Chapter 3. Fundamentals of Digital Logic Circuit Design.- Chapter 4. Design A Single-cycle CPU.- Chapter 5. Design A Simple Pipelined CPU.- Chapter 6. AddMore User Mode Instructions into Pipeline.- Chapter 7. Support Exception and Interrupt.- Chapter 8. AXIBus Interface Design.- Chapter 9. Storage Management Unit Design.- Chapter 10. Cache Design.- Chapter 11. Advanced Experimental Environments.- Chapter 12. Advanced Design.